64Kbit asynchronous SRAM in a 28-pin DIP
The CY7C185-20PC is a 64Kbit asynchronous SRAM organized as 8K x 8 bits, with a 20 ns access time.
A 20 ns access time means the SRAM can complete a read cycle within 20 ns of the address being valid. This speed grade suits legacy 8-bit microcontrollers and DSPs with bus cycles in the 30–50 ns range, providing adequate setup margin. At 5V ±10% the part delivers consistent timing; derating at lower supply voltages is minimal for this family.
Obsolete — sourcing for production and repair
For new designs, a pin-compatible 64Kbit asynchronous SRAM in a 28-pin DIP from another manufacturer should be evaluated.
