Obsolete 16Kbit asynchronous SRAM in a 20-DIP footprint
The CY7C168A-20PXC: Housed in a 20-pin DIP (0.300", 7.62mm) package, this part was designed for legacy 5 V logic systems requiring fast scratchpad or configuration storage.
In a system with a 5 V bus running at 25 MHz (40 ns cycle), this leaves 20 ns of margin for address decoding, buffer delays, and setup time to the controller — adequate for most legacy glue-logic designs but tight if cascading multiple memory banks without pipeline registers.
Sourcing is limited to surplus inventory and broker channels.
The 20-DIP (0.300", 7.62mm) through-hole package suits socketed prototyping or retrofit into existing PCB layouts with a 0.3" row spacing.
