144 Mbit QDR II SRAM — 333 MHz pipeline for high-throughput buffers
It clocks at 333 MHz on a parallel interface, delivering read and write on every rising and falling edge — four data words per clock cycle.
At 333 MHz the QDR II interface sustains a peak data rate of 2.664 Gbps per 36-bit word (assuming DDR on both read and write ports).
Package and board integration — 165-FBGA, 15x17 mm
The 165-ball FBGA (15x17 mm) footprint requires a multilayer PCB with microvias or staggered vias for fanout. The part ships in Tray — typical for BGA parts that go through pick-and-place in production.
