It clocks at 300 MHz on a parallel interface, delivering back-to-back read and write operations on separate ports with no dead cycles — the defining advantage of the QDR II family over standard synchronous SRAMs.
At 300 MHz the QDR II interface delivers a double-data-rate transfer on each port. The 36-bit data bus width moves 36 bits per clock edge.
Package and mounting — 165-FBGA
It is surface-mount only, requiring a reflow profile compatible with BGA assembly. The 15x17 mm body size means the PCB footprint should follow the manufacturer's land pattern recommendations.
