633 MHz DDR II+ SRAM — 72 Mbit wide-word buffer for high-throughput designs
Organized as 2M x 36, it delivers a 36-bit wide data path per access — a natural fit for networking packet buffers, telecom line cards, and test equipment that move wide words without external byte-lane muxing.
The 633 MHz clock rate is the headline performance spec. In a DDR II+ SRAM, data is transferred on both edges of the clock, so the effective data rate is 1.266 G transfers per second per pin. For a 36-bit-wide bus, that translates to roughly 45.6 Gbps of raw bandwidth — enough to keep a high-end FPGA or network processor fed without wait states. The trade-off is tighter signal-integrity requirements on the PCB: the 165-ball FBGA (13x15 mm) demands controlled-impedance routing and adequate decoupling close to the supply balls.
Package and footprint — 165-FBGA (13x15 mm)
The 1.7V to 1.9V core supply means the PCB power plane should be sized for the peak current draw at 633 MHz — a typical DDR II+ SRAM at this speed pulls several hundred mA during active bursts.