72 Mbit QDR II+ SRAM at 366 MHz — the bandwidth ceiling for wide-word pipelines
The CY7C1564XV18-366BZC is a 72 Mbit synchronous SRAM organized as 2M x 36, using the QDR II+ architecture — quad-data-rate means it transfers four words per clock cycle on separate read and write ports, so the 366 MHz clock delivers a peak bandwidth of 14.6 Gbit/s on the 36-bit datapath.
Available through independent distribution channels; quantities are lot-specific and confirmed at RFQ. No pin-compatible drop-in replacement from Infineon is documented, so a board-level redesign is required if migrating to a current-production SRAM family.