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Infineon Technologies CY7C1513KV18-250BZXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1513KV18-250BZXI QDR II SRAM, 72Mbit, 250 MHz

MPNCY7C1513KV18-250BZXI
Active

Infineon Technologies CY7C1513KV18-250BZXI, QDR II synchronous SRAM, 72Mbit (4M x 18), 250 MHz clock, 1.7-1.9V, -40 to 85°C, 165-FBGA (13x15), Tray.

$165.1125Ref. price · indicative, final on quote
Infineon Technologies CY7C1513KV18-250BZXI datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1513KV18-250BZXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Clock frequency250 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, QDR II
Memory size72Mbit
Memory formatSRAM
Case165-LBGA
Memory organization4M x 18

Product details

QDR II SRAM — 72 Mbit at 250 MHz

The Infineon CY7C1513KV18-250BZXI is a 72 Mbit Quad Data Rate (QDR) II synchronous SRAM organized as 4M x 18 bits. It clocks at 250 MHz, delivering back-to-back read and write operations on every rising and falling edge of the clock — effectively doubling the data throughput per pin compared to a single-data-rate SRAM at the same frequency.

The 165-LBGA supplier device package (13x15 mm) requires a multi-layer PCB for signal fan-out and decoupling; the core supply rail at 1.7-1.9 V needs local bypass caps within 5 mm of the BGA balls to keep supply noise under 50 mV peak-to-peak at 250 MHz.

Infineon lists the CY7C1513KV18-250BZXI as Active (current production). The base product number CY7C1513 covers the full family of 72 Mbit QDR II SRAMs with varying speed grades and temperature ranges. The -250BZXI suffix denotes the 250 MHz speed grade, industrial temperature, and 165-FBGA package in tray format.

Frequently asked questions

What is the memory organization and clock speed of this QDR II SRAM?

The CY7C1513KV18-250BZXI is organized as 4M x 18 bits (72 Mbit total) and operates at a 250 MHz clock frequency. As a QDR II device, it transfers data on both clock edges, achieving an effective 500 MHz data rate on the I/O pins.