It clocks at 250 MHz on a parallel interface, delivering back-to-back read and write transactions every cycle — no dead cycles between bus turns, which is what the QDR (Quad Data Rate) protocol buys you. Packaged in a 165-ball FBGA (15x17 mm), it surface-mounts and requires the usual BGA reflow profile and X-ray inspection.
Obsolete — last-time-buy and sourcing path
Infineon has discontinued production — no further factory orders are accepted. If you have an active BOM line using this SRAM, the procurement decision is immediate: secure inventory for your remaining build window or qualify a replacement.
The 250 MHz clock rate on a QDR II interface supports back-to-back read and write transactions every cycle.