Skip to main content
Infineon Technologies CY7C1512V18-167BZXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1512V18-167BZXC QDR II SRAM 72Mbit 167MHz

MPNCY7C1512V18-167BZXC
Obsolete

Infineon Technologies CY7C1512V18-167BZXC, QDR II synchronous SRAM, 72Mbit, 4M x 18 organization, 167 MHz clock, 1.7V-1.9V supply, 165-FBGA, tray.

$119.4500Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1512V18-167BZXC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTray
TechnologySRAM - Synchronous, QDR II
Memory size72Mbit
Memory formatSRAM
Case165-LBGA
Memory organization4M x 18

Product details

The CY7C1512V18-167BZXC is a 72 Mbit synchronous SRAM organised as 4M x 18 bits, using the QDR II (Quad Data Rate) architecture with a separate read and write port. The 167 MHz clock frequency means the memory delivers a peak data rate of 334 million transfers per second per port — the QDR II interface eliminates the bus-turnaround penalty of common-I/O SRAM, so a network processor or packet buffer can read and write on every clock edge without dead cycles. The parallel interface and 1.7 V to 1.9 V supply rail place it in the low-voltage synchronous SRAM class, designed for high-throughput applications where a DDR or QDR bus matches the controller's memory controller natively.

The supplier device package (165-FBGA) is the same footprint as other Cypress/Infineon 72 Mbit QDR II parts, so a board already laid out for a sibling density can accept this part without a respin — provided the supply voltage and temperature grade match.

Temperature grade and environment

It is not qualified for industrial or automotive ambient extremes — a design requiring -40°C to +85°C operation needs the industrial-grade variant from the same family.

Lifecycle reality — obsolete and how to source it

For existing BOM lines that require this exact part number, the supply path runs through independent distribution and surplus channels. Date-code provenance and lot traceability should be verified before committing to a production run.

Frequently asked questions

What is the memory organization of CY7C1512V18-167BZXC?

It is organised as 4M x 18 bits, giving a total density of 72 Mbit. The QDR II architecture provides separate read and write ports, each operating at the 167 MHz clock rate.