The CY7C1512KV18-200BZXC: It clocks at 200 MHz on the parallel interface, delivering back-to-back read and write bursts without dead cycles — the defining advantage of the QDR II protocol over traditional DDR SRAM.
200 MHz clock and QDR II — what the throughput means for the bus
At 200 MHz the QDR II interface delivers back-to-back read and write bursts without dead cycles, using separate read and write ports.
