72Mbit QDR II SRAM at 250 MHz — what the bus wants
Organized 4M x 18, it clocks at 250 MHz, which means back-to-back read-write throughput without idle cycles. That architecture is why this part shows up in high-performance networking buffers, telecom line cards, and test equipment where every clock edge carries data.
Industrial temperature — not just a lab part
The 250 MHz clock holds across that range, but the timing budget tightens at temperature extremes — a signal-integrity simulation at the cold corner is worth the time before layout freeze.
Obsolete — sourcing reality for this BOM line
Infineon lists this part as obsolete. No official successor order code is available.