72Mbit synchronous SRAM — 250 MHz pipeline
The CY7C1484BV25-250AXI is a 72 Mbit synchronous SRAM organized as 2M x 36 bits, clocked at 250 MHz with a 3 ns access time from clock edge.
100-TQFP footprint and board-fit
Housed in a 100-lead TQFP (14 x 20 mm body, 0.50 mm pitch), the part requires a standard surface-mount reflow profile with MSL handling per the package moisture sensitivity — the exposed pad is not present on this TQFP variant, so thermal dissipation relies on the leadframe and board copper. The parallel memory interface (address, data, control) routes directly to a processor or FPGA memory controller; the 36-bit data bus width suits 32-bit plus parity or ECC implementations.