For production builds, the BOM line needs a validated replacement or a last-time-buy bridge through independent distribution. No official successor part is listed on the record, so pin-compatible alternatives must be qualified from the broader NoBL family or a second-source vendor.
200 MHz clock, 3 ns access — the bus timing decision
This is a 72Mbit synchronous SRAM organized as 4M x 18, clocked at 200 MHz with a 3 ns access time. The 3 ns access time means the output data is valid within 3 ns of the clock edge, which tightens the timing closure budget on a 200 MHz bus; the board designer should verify setup/hold margins against the FPGA or ASIC interface.
Package and temperature — where it fits
Housed in a 100-TQFP (14x20 mm) package, surface-mount, with a parallel memory interface. Supply voltage range is 3.135V to 3.6V, a standard 3.3V nominal rail with margin for ripple.