72 Mbit NoBL synchronous SRAM at 200 MHz
It clocks at 200 MHz with a 3 ns access time, operating from a 2.375 V to 2.625 V supply. This part is intended for high-throughput data buffering, cache, and packet memory in networking, telecom, and server applications where back-to-back read-write throughput matters.
200 MHz clock and 3 ns access — timing budget
At 200 MHz the clock period is 5 ns. With a 3 ns access time, the output data is valid 3 ns after the clock edge, leaving 2 ns of setup and hold margin for the receiving device. This is tight but workable with modern FPGAs and ASICs that have programmable I/O delays. The 2.5 V supply is specific — do not assume 3.3 V or 1.8 V compatibility; the core and I/O share the same 2.5 V rail, so a clean 2.5 V regulator with ±5% tolerance is required.
NoBL architecture — throughput advantage
Standard synchronous SRAMs insert a dead cycle when switching from read to write (or write to read). The NoBL pipeline allows consecutive read-write-read operations without idle cycles, delivering full 200 MHz throughput on mixed transactions. This matters in packet processing where the bus alternates between reading descriptors and writing data.
Housed in a 100-TQFP (14x20 mm) package with surface-mount footprint.