133 MHz pipeline — NoBL eliminates dead cycles
The CY7C1471V33-133AXCT is a 72Mbit synchronous SRAM organized as 2M x 36, clocked at 133 MHz with a 6.5 ns access time. The NoBL (No Bus Latency) pipeline lets the controller issue a new read address on every rising clock edge without inserting idle cycles between back-to-back reads — a key advantage for high-throughput packet buffers in networking gear or telecom line cards where every clock cycle counts.
Supply and temperature — single 3.3V rail, commercial range
Housed in a 100-LQFP (supplier device package 100-TQFP, 14x20 mm) — a standard fine-pitch quad flat pack that is rework-friendly with a hot-air station and does not require X-ray inspection like a BGA.
Obsolete — sourcing through independent surplus channels
Availability is limited to independent surplus and broker inventory — quantities are lot-specific and confirmed at RFQ. No pin-compatible drop-in replacement is documented; a board spin may be required if migrating to a different SRAM family.