72Mbit NoBL SRAM for high-throughput data paths
It runs at a 133 MHz clock with a 6.5 ns access time, meaning the memory can deliver a new 36-bit word every clock cycle without inserting dead cycles between read and write turns. The 36-bit word width is worth noting — it maps cleanly to a 32-bit datapath with four parity bits, or to a 36-bit wide memory bus without external byte-lane muxing. Supply range is 3.135V to 3.6V, which aligns with standard 3.3V logic families.
6.5 ns access — timing margin for the system architect
At a 133 MHz clock (7.5 ns period), this leaves about 1 ns of setup margin before the next rising edge — tight but workable with controlled impedance traces and matched-length routing on the address/control bus. If your FPGA or ASIC interface has a setup time of 1.5 ns or more, you may need to add a wait state or reduce clock frequency. Budget the PCB flight time and clock skew into that margin.
No Bus Latency — what it saves you
Standard synchronous SRAMs insert one dead cycle when switching from read to write (or write to read). The NoBL architecture eliminates that turnaround penalty, so a read immediately followed by a write completes in two clocks instead of three. In a 133 MHz system that saves 7.5 ns per transaction — meaningful for burst-oriented traffic like cache line fills or descriptor ring updates.
Housed in a 100-lead TQFP (14x20 mm body), the part is surface-mount and suited for standard reflow assembly.
That means no last-time-buy pressure for ongoing builds.