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Infineon Technologies CY7C1471BV33-133AXC — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1471BV33-133AXC 72Mbit SRAM, 133 MHz, 2M x 36

MPNCY7C1471BV33-133AXC
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Infineon Technologies CY7C1471BV33-133AXC, NoBL™ series, Synchronous SRAM, 72Mbit, 2M x 36, 133 MHz, 6.5 ns, 3.135V-3.6V, 100-TQFP, Tray.

$128.6651Ref. price · indicative, final on quote
Infineon Technologies CY7C1471BV33-133AXC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1471BV33-133AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency133 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time6.5 ns
Memory size72Mbit
Memory formatSRAM
Case100-LQFP
Memory organization2M x 36

Product details

72 Mbit synchronous SRAM — 133 MHz, 2M x 36, NoBL™ pipeline

The CY7C1471BV33-133AXC is a 72 Mbit synchronous SRAM from Infineon's NoBL™ family, organized as 2M words by 36 bits. The 133 MHz clock rate and 6.5 ns access time mean the part can sustain back-to-back reads or writes without dead cycles — the NoBL™ pipeline eliminates the turnaround latency typical of conventional synchronous SRAMs.

Supply voltage and temperature grade — what they mean for fit

This part will not work on a 1.8 V or 2.5 V core supply without a level translator on the address and data lines. If the system sees ambient above 70 °C or below freezing, this part is out of spec — an industrial-temperature variant would be needed.

Package and board integration — 100-TQFP (14x20 mm)

Housed in a 100-lead TQFP (14x20 mm body), the part is surface-mount with a fine-pitch leadframe. The 0.5 mm pitch demands a controlled soldering profile and careful PCB layout to avoid bridging. The package is not moisture-sensitive per JEDEC Level 3, but a bake before reflow is recommended if the shelf life has been exceeded.

Frequently asked questions

What is the memory organization and bus width of CY7C1471BV33-133AXC?

The part is organized as 2M words by 36 bits, giving a total of 72 Mbit. The 36-bit wide parallel interface includes 4 parity/ECC bits per word, which is useful for systems that need single-bit error correction on the fly.

What is the NoBL™ series and how does it affect performance?

NoBL™ (No Bus Latency) is a pipelined synchronous SRAM architecture that eliminates the dead cycle between read and write operations. At 133 MHz, this means the memory controller can issue a write immediately after a read without waiting, improving throughput in high-bandwidth data paths.