72 Mbit NoBL synchronous SRAM at 167 MHz
The CY7C1470V33-167BZXC: The NoBL architecture eliminates dead bus cycles between read and write operations, sustaining full-throughput back-to-back transactions without wait states — critical for high-performance cache, deep FIFO buffers, and network packet memory where every clock cycle counts.
The 167 MHz clock rate and 3.4 ns access time set the speed grade for this synchronous SRAM.
2M x 36 organization — word width for wide datapaths
The 2M depth by 36-bit width organization suits systems that move 36-bit words per transaction.
The CY7C1470V33-167BZXC is marked obsolete by Cypress (now Infineon). Buyers should expect limited and declining availability.
165-FBGA — fine-pitch BGA handling
The 165-FBGA package measures 15x17 mm with a fine-pitch ball array.