72 Mbit synchronous SRAM — 167 MHz pipeline with NoBL architecture
The CY7C1470V33-167BZI: It belongs to Cypress's NoBL™ (No Bus Latency) family, where the pipeline eliminates dead cycles between reads and writes — the next transaction starts on the clock edge after the previous one completes, without an idle turn-around cycle.
Package and board-fit — 165-ball LBGA, 15x17 mm
The 165-LBGA (15x17 mm FBGA) package uses a 1.0 mm ball pitch typical of Cypress high-density synchronous SRAMs. The supply decoupling plan should follow the recommended layout in the datasheet: place 0.1 µF and 1 µF MLCCs within 3 mm of each VDDQ and VDD ball pair, with a bulk 10 µF tantalum near the package edge. The centre ground balls on the 15x17 array handle return current for the 36-bit data bus.
Active lifecycle — no EOL watch for new designs
Infineon lists the CY7C1470V33-167BZI as Active (current production). This part is suitable for both new-design-in and sustaining production without a last-time-buy window.
No stock-holding claim; the part is quoted to order with full traceability back to the Infineon/Cypress wafer lot.