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Infineon Technologies CY7C1470V33-167AXI — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1470V33-167AXI Infineon NoBL SRAM, 72Mbit, 167 MHz

MPNCY7C1470V33-167AXI
Active

Infineon Technologies NoBL™ SRAM, synchronous SDR, 72Mbit, 167 MHz clock, 3.4 ns access, 2M x 36 organization, 3.3V supply, 100-LQFP surface mount, -40 to 85°C.

$265.2650Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1470V33-167AXI specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3.4 ns
Memory size72Mbit
Memory formatSRAM
Case100-LQFP
Memory organization2M x 36

Product details

72Mbit synchronous SRAM for high-throughput data buffers

The CY7C1470V33-167AXI is a 72Mbit synchronous pipelined SRAM from Infineon's NoBL™ family, organized as 2M x 36 bits. The parallel interface keeps the bus simple for FPGA or ASIC integration without the serialization overhead of QSPI or HyperBus.

100-TQFP package — board integration note

The 100-LQFP package is supplied as a 100-TQFP (14x20 mm) — a 0.5 mm pitch fine-pitch quad flat pack. The footprint requires a controlled impedance PCB stack-up for the 36-bit data bus at 167 MHz; signal integrity on the parallel bus depends on matched trace lengths and proper VTT termination on the address/control lines.

Frequently asked questions

Where can I buy the CY7C1470V33-167AXI and what is the lead time?

The CY7C1470V33-167AXI is sourced to order through independent distribution against an RFQ — availability and current pricing are confirmed at quote time. Given the eol_hot lifecycle classification, independent stock on the broker market is finite; qualify sourcing early to avoid line-down exposure.

What is the NoBL series designation on the CY7C1470V33-167AXI?

NoBL (No Bus Latency) is Infineon's SRAM architecture optimized to eliminate read-data turnaround delay on the bus, which improves bandwidth utilization in applications with frequent bidirectional bus traffic.