It clocks at 167 MHz and delivers a 3.4 ns access time, eliminating the dead bus cycles typical of pipelined SRAMs.
Obsolete — sourcing reality for sustainment programs
For sustainment of existing designs — telecom infrastructure, legacy test equipment, or military/aerospace systems that qualified this specific SRAM — the procurement path runs through independent distribution.
NoBL™ architecture — why the bus stays busy
Standard synchronous SRAMs insert a dead cycle when switching from read to write (or write to read). The NoBL™ pipeline allows the next access to begin immediately, regardless of direction. At 167 MHz, that saves one clock cycle per transaction — meaningful in a 72 Mbit buffer handling mixed read/write traffic.
Package and footprint — 100-TQFP (14x20 mm)
The CY7C1470V33-167AXCT is supplied in a 100-TQFP package (14x20 mm body, 0.5 mm pitch). It is a surface-mount, leaded package suitable for standard reflow assembly.