Skip to main content
Infineon Technologies CY7C1470BV33-200BZXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1470BV33-200BZXI SRAM, 72Mbit, 200MHz, 165-LBGA

MPNCY7C1470BV33-200BZXI
Active

Infineon Technologies NoBL™ SRAM, Synchronous SDR, 72Mbit, 2M x 36, 200 MHz, 3 ns, 3.135-3.6 V, -40 to 85 °C, 165-LBGA, Tray.

$189.4200Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1470BV33-200BZXI specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency200 MHz
Memory interfaceParallel
Operating temperature-40°C~85°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3 ns
Memory size72Mbit
Memory formatSRAM
Case165-LBGA
Memory organization2M x 36

Product details

72Mbit synchronous SRAM — speed-grade and board-fit

The CY7C1470BV33-200BZXI is a 72Mbit synchronous SRAM from the NoBL™ family, organized as 2M x 36, clocked at 200 MHz with a 3 ns access time. That 200 MHz clock rate means the part can sustain back-to-back read/write transactions without dead cycles — the NoBL pipeline hides the address-bus turn-around that older synchronous SRAMs leave exposed. The 3 ns access time is the delay from clock edge to valid data on the bus; at 200 MHz the clock period is 5 ns, so the data arrives well within the next cycle, leaving margin for board trace delay and the FPGA or ASIC's input setup time.

Housed in a 165-ball LBGA (15x17 mm body), the part is a surface-mount BGA. The -BZXI suffix indicates lead-free (RoHS) and industrial temp; no separate bake or moisture-sensitive-level (MSL) rating is listed here, but BGA packages typically require MSL 3 handling per JEDEC J-STD-020.

Active lifecycle and sourcing

Infineon lists the CY7C1470BV33-200BZXI as Active (current production).

Frequently asked questions

Where can I buy CY7C1470BV33-200BZXI and get a price?

Submit a request for quote to confirm current availability and pricing.

What is the memory organization of CY7C1470BV33-200BZXI?

It is organized as 2M words by 36 bits (2M x 36), giving a total density of 72 Mbit. The 36-bit word width is typical for designs needing parity or ECC alongside a 32-bit data bus.