For existing designs still needing this exact order code, supply is limited to surplus and broker inventory.
3 ns access time at 200 MHz — the performance envelope
The 200 MHz clock and 3 ns access time eliminate dead cycles between read and write turns, delivering back-to-back throughput that matters in networking packet buffers, telecom line cards, and high-end test equipment. The 72 Mbit density organized as 2M x 36 gives a 36-bit data bus width, sized for 32-bit word plus parity or ECC overhead.
The 165-LBGA (15x17 mm) package is a fine-pitch BGA; boards designed for this footprint need the same ball map as the 165-FBGA variant.