At 200 MHz the clock period is 5 ns, and the 3 ns access time leaves 2 ns for board trace delay, clock skew, and setup hold at the controller. That is a tight but workable margin for a point-to-point SRAM link on a well-laid-out PCB. The 2.5 V I/O swings faster than 3.3 V, which helps edge rates but also reduces noise margin — keep the supply clean and the decoupling tight.
Procurement must source through the surplus and broker channel.
Housed in a 165-ball FBGA (15x17 mm body), surface-mount only.
