36 Mbit synchronous SRAM at 250 MHz — what the clock and access time mean for your bus
The CY7C1462BV25-250BZXC is a 36 Mbit synchronous SRAM organized as 2M x 18, clocked at 250 MHz with a 2.6 ns access time from the clock edge to data-out. This is a NoBL (No Bus Latency) part — the pipeline architecture hides the turnaround cycle between read and write, so the bus stays at full throughput without dead cycles when the controller flips direction. The 165-FBGA (15x17 mm) footprint is the same ballout as the standard 165-ball Cypress SRAM layout — a board already routed for that pattern accepts this part without a respin.
Infineon lists the CY7C1462BV25-250BZXC as Obsolete. Availability, date codes, and condition (new original, reels, or trays) are confirmed at quote time. No stock-holding claim is made — the supply posture is per-request verification.
Package and board-fit — 165-FBGA landing pattern
The 165-LBGA alternative designation refers to the same mechanical outline. The tray packaging is standard for this class of BGA memory. The base product number CY7C1462 covers the 2M x 18 organization across speed grades and temperature ranges. The -250 suffix selects the 250 MHz clock rate; the BZXC suffix encodes the 165-FBGA package and commercial temperature range.