36 Mbit NoBL SRAM for high-throughput pipelines
The CY7C1462AV33-167AXC: It clocks at 167 MHz with a 3.4 ns access time, meaning back-to-back reads and writes happen without dead cycles on the bus — critical for high-throughput data buffers in networking, base stations, and test equipment where every clock cycle counts.
If you are stocking spares for a legacy board, this is the kind of part to buy ahead on when you see a lot.
The 167 MHz clock rate and 3.4 ns access time are the headline specs. The NoBL pipeline eliminates the turnaround cycle between read and write.
