36 Mbit NoBL synchronous SRAM for high-throughput data paths
Clocked at 133 MHz with a 6.5 ns access time, it keeps the pipeline full in cache-line fills and packet buffers where every bus cycle counts.
At 133 MHz the clock period is roughly 7.5 ns, and the 6.5 ns access time leaves about 1 ns of setup margin before the next clock edge. That's tight but workable with controlled-impedance traces and proper termination on the parallel bus. If you're running a 100 MHz bus instead, the margin opens up to around 3.5 ns, which simplifies the PCB layout and lets you skip series resistors on shorter lines.
NoBL architecture — no dead cycles on mixed transactions
Standard synchronous SRAMs insert an idle cycle when switching from read to write (or vice versa). The NoBL design lets the controller issue a write on the cycle immediately after a read without a bubble. In a system doing interleaved read-modify-write operations—like a network processor updating statistics counters—that saves one clock per transaction, which at 133 MHz is 7.5 ns saved each time. The throughput gain adds up fast in high-port-count designs.
Supply rail and temperature range — what the board sees
The 3.135V to 3.6V supply covers a nominal 3.3V rail with ±5% tolerance, which is standard for most FPGA and ASIC banks. If your board runs a 3.0V core rail, this part won't work without a separate 3.3V supply.
Package and footprint — 100-TQFP (14x20 mm)
The 100-TQFP package with a 14x20 mm body and 0.5 mm pitch is a common footprint shared by many synchronous SRAMs in the 36 Mbit density class. It's a surface-mount package that reflows with standard lead-free profiles. The tray shipping medium means it arrives in antistatic trays, not tape-and-reel — something to note if your pick-and-place feeder setup expects reels.
The base product number CY7C1461 covers a family of density and speed variants, so if you later need a faster or slower grade, the pinout stays the same across the 100-TQFP options.