Active production, 250 MHz NoBL SRAM for wide-bus throughput
It delivers a 250 MHz clock frequency with a 2.5 ns access time, eliminating the dead cycle between read and write operations that standard pipelined SRAMs require.
NoBL architecture — what the 250 MHz clock buys you
Standard synchronous SRAMs insert a turnaround cycle when switching from read to write, wasting a clock edge. The NoBL pipeline lets the bus transition without a dead cycle, so at 250 MHz the effective data rate approaches the full clock rate on mixed read/write traffic. For a 36-bit-wide bus, that is 9 Gbit/s of sustained bandwidth — the difference between meeting a line-rate packet buffer budget and falling short by one cycle. At 250 MHz (4 ns period), that leaves 1.5 ns of setup margin before the next clock edge — tight, but workable with controlled-impedance traces and proper termination. The 36-bit organization maps cleanly to a 32-bit data bus plus parity or ECC bits without needing two devices.