36 Mbit NoBL synchronous SRAM — 200 MHz, 3.2 ns access
The NoBL architecture eliminates the dead bus cycles typical of traditional synchronous SRAMs by allowing back-to-back read and write operations without turnaround cycles, which directly improves throughput in high-bandwidth applications like network buffers, telecom line cards, and high-end compute accelerators.
200 MHz clock and 3.2 ns access — timing budget for the bus
The 200 MHz clock rate sets a 5 ns cycle window. The 3.2 ns access time leaves 1.8 ns of slack for the controller's setup and hold, PCB trace delay, and signal-integrity margin. A system architect clocking a 200 MHz memory controller must verify that the combined FPGA/ASIC output delay plus board propagation fits inside that window — otherwise, the next speed grade (if available) or a flow-through pipeline stage is needed. The parallel memory interface (36-bit data bus) matches well with 32-bit or 36-bit controllers; the 1M word depth gives 4 MB of addressable space per chip.
The base product number CY7C1460 covers multiple speed and package variants; the -200AXC suffix selects the 200 MHz speed grade in a 100-TQFP (14x20) package, tray delivery. No official successor or second-source alternate is recorded in the sourcing data, so the BOM depends on this exact order code for fit.