36Mbit NoBL SRAM — throughput without bus dead cycles
The CY7C1460KV33-167BZC is a 36Mbit synchronous SRAM organized as 1M x 36, part of Infineon's NoBL (No Bus Latency) series. The NoBL architecture eliminates the dead cycle between read and write operations on the same bus — the memory accepts a new command every clock cycle regardless of the previous operation's direction. Rated for a 167 MHz clock, the part delivers a peak data rate of 167 million 36-bit words per second. The 3.4 ns access time from address to data valid sets the latency floor for cache-line fills and look-up-table reads.
Operates from a 3.135V to 3.6V supply, making it directly compatible with 3.3V nominal systems without an external regulator. Packaged in a 165-ball FBGA (15x17 mm body). The fine-pitch BGA footprint requires controlled impedance routing on the data and address lines; the 36-bit parallel interface demands careful signal-integrity simulation at 167 MHz to avoid setup/hold violations across the bus.