Active production — quoted to order
The CY7C1460KV33-167AXIT: Infineon lists this part as Active.
36 Mbit synchronous SRAM — clock ceiling and bus timing
The 167 MHz clock rate sets the maximum bus throughput — the controller must match this cycle time on the memory bus. Access time is 3.4 ns; that figure governs the read-to-data-valid window and determines whether a slower FPGA or ASIC memory controller can close timing without wait states. Part of the NoBL™ series, which eliminates the dead bus cycle between read and write operations. In a pipelined system this means back-to-back transactions without a turnaround cycle — relevant for packet buffers or trace buffers where every clock edge carries a valid transfer.
Package — 100-LQFP, Tape & Reel
Supplied in a 100-lead LQFP with a body size of 14 x 20 mm. The 0.5 mm pitch demands a PCB with at least four layers for fan-out; the exposed pad on the TQFP variant improves thermal conduction to the board plane. Tape & Reel packaging suits automated pick-and-place assembly.