Infineon Technologies NoBL™ SRAM, synchronous SDR, 36Mbit, 1M x 36, 167 MHz, 3.4 ns, 3.135V-3.6V, 0°C-70°C, 100-TQFP (14x20), Tape & Reel.
| Parameter | Value |
|---|---|
| Series | NoBL™ |
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 3.135V ~ 3.6V |
| Clock frequency | 167 MHz |
| Memory interface | Parallel |
| Operating temperature | 0°C~70°C(TA) |
| Package | Tape & Reel (TR) |
| Technology | SRAM - Synchronous, SDR |
| Access time | 3.4 ns |
| Memory size | 36Mbit |
| Memory format | SRAM |
| Case | 100-LQFP |
| Memory organization | 1M x 36 |
The CY7C1460KV33-167AXCT: The NoBL (No Bus Latency) architecture eliminates the dead cycles between back-to-back reads common in pipelined SRAMs, so the controller sees zero-wait-state throughput on sequential accesses — a meaningful gain for cache-line fills or packet buffers.
It is organized as 1M x 36 bits, giving 36 Mbit total density.