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Infineon Technologies CY7C1460KV33-167AXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1460KV33-167AXC NoBL SRAM, 36 Mbit, 167 MHz, 3.3 V

MPNCY7C1460KV33-167AXC
Active

Infineon (Cypress) CY7C1460KV33-167AXC NoBL™ synchronous SRAM, 36 Mbit (1M x 36), 167 MHz clock, 3.4 ns access, 3.135–3.6 V supply, 0°C–70°C, 100-TQFP (14x20 mm), parallel interface, tray.

$48.6184Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1460KV33-167AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency167 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3.4 ns
Memory size36Mbit
Memory formatSRAM
Case100-LQFP
Memory organization1M x 36

Product details

36 Mbit NoBL synchronous SRAM — 167 MHz pipeline for high-throughput data buffers

The CY7C1460KV33-167AXC is a 36 Mbit synchronous SRAM from Infineon (Cypress) in the NoBL™ (No Bus Latency) family, organized as 1M x 36 and clocked at 167 MHz.

167 MHz clock and 3.4 ns access — what they mean for bus timing

The 167 MHz clock rate defines the maximum data rate on the parallel bus: one 36-bit word per clock cycle, or roughly 667 MB/s peak bandwidth. The 3.4 ns access time is the delay from the clock edge to valid data on the outputs; this window must be accommodated by the memory controller's setup time, so a 3.4 ns access at 167 MHz (6 ns period) leaves about 2.6 ns of margin for PCB trace delay and input hold — workable on a well-terminated bus, but tight for long backplane traces. The NoBL architecture eliminates the dead cycle normally required when switching from read to write, so the bus stays fully utilised in mixed-transaction patterns.

1M x 36 organisation — wide-word fit and routing impact

The 1M x 36 organisation presents a 36-bit data word on each access, which maps directly to 36-bit processor buses or can be split into two 18-bit banks for dual-channel use. The trade-off is pin count: the 100-pin TQFP package dedicates 36 pins to data, plus address, control, and power — routing a 36-bit bus on a two-layer board is challenging; a four-layer stack-up with a solid ground plane is the practical minimum. The 100-TQFP (14x20 mm) body is a standard JEDEC footprint, so layout guides for other Cypress/Infineon 100-pin synchronous SRAMs apply directly.

It is not specified for industrial enclosures, outdoor base stations, or automotive cabin applications where ambient can reach 85°C or higher. If the end system must operate below freezing or above 70°C, an industrial-temperature variant (typically -40°C to 85°C) from the same NoBL family would be required — verify pin compatibility against the datasheet.

Infineon lists the CY7C1460KV33-167AXC as Active (current production). For new designs, this part carries no supply-risk flag from the manufacturer side. The base product number CY7C1460 covers a range of density and speed options; if the 36 Mbit / 167 MHz variant is the fit, it remains a supported choice for production builds.

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