200 MHz NoBL SRAM for wide-word data paths
It runs at a 200 MHz clock frequency and delivers a 3.2 ns access time, which means back-to-back read and write transactions can proceed without dead cycles on the bus — the NoBL architecture eliminates the turnaround cycle that older pipelined SRAMs need when switching from read to write.
3.2 ns access at 200 MHz — the timing budget
At 200 MHz the clock period is 5 ns. With a 3.2 ns access time from clock edge to data valid, the memory controller has roughly 1.8 ns of setup margin before the next clock edge — assuming zero board delay. That margin shrinks fast with trace length, so the layout needs tight fly-by routing and matched-length traces between the SRAM and the controller. The 2.375 V to 2.625 V supply range is a 2.5 V nominal rail; a clean 2.5 V supply with <5% ripple is expected to hold the timing numbers.
The 165-FBGA footprint is a 15x17 ball array with a 1.0 mm pitch — a standard layout for high-pin-count synchronous memories. The tray shipping medium means the parts arrive in antistatic trays, not tape-and-reel; factor that into your pick-and-place feeder setup if you are running high-volume lines.
The part is RoHS-compliant as a standard lead-free device. No AEC-Q100 qualification is listed, so this is an industrial/commercial grade part, not automotive-rated.