36Mbit NoBL SRAM with 167 MHz pipeline
It clocks at 167 MHz with a 3.4 ns access time, operating from a 2.375V to 2.625V core supply. The NoBL architecture eliminates dead cycles between read and write turns, sustaining full pipeline throughput on every clock edge — a fit for high-bandwidth packet buffers, cache tag stores, and network processor look-aside memory.
Industrial temperature and BGA footprint
The 165-ball FBGA (15x17 mm) demands a controlled reflow profile — MSL level should be verified from the date code, and the balls need a clean pad finish for reliable solder joint formation. The 2.5V supply rail is tighter than a 3.3V SRAM, so the board regulator must hold within 2.375V to 2.625V under load transients.
Last Buy — plan the LTB now
This part carries a Last Buy status. That means Cypress has scheduled the final production run — the window to place a last-time-buy order is open but finite. Once the LTB window closes, the part will be unavailable through authorized channels. If your BOM still depends on this exact density and speed grade, secure the LTB quantity for your remaining build plan. For post-LTB needs, you will be sourcing from the independent market, where pricing and availability are quoted per RFQ.
3.4 ns access — timing margin in the pipeline
The 3.4 ns access time at 167 MHz gives roughly one clock period (6 ns) minus setup/hold for the receiving logic. In a 2.5V I/O domain, that leaves about 2.6 ns of timing budget for PCB trace delay and clock skew — enough for a well-laid-out board, but marginal if the SRAM sits far from the controller. Keep the trace length under 50 mm and match the clock-to-data delays within 0.5 ns to avoid setup violations at speed.