36 Mbit synchronous SRAM for high-throughput buffers
It runs at a 250 MHz clock frequency with a 2.6 ns access time, eliminating dead cycles between read and write turns on a shared bus.
Obsolete — plan for a replacement or surplus buy
Cypress has discontinued production, so new-design insertion is not possible through the factory channel. For existing BOM lines, the procurement path is surplus inventory or a last-time-buy from independent distribution.
The 250 MHz clock rate sets the maximum throughput at 1 Gbyte/s on a 36-bit wide bus (assuming one transfer per cycle). That margin shrinks with PCB trace delay and capacitive loading — keep the trace length short and match impedances to avoid hold-time violations.
Housed in a 100-pin TQFP (14x20 mm body), surface-mount only.