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Infineon Technologies CY7C1460AV33-200AXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C1460AV33-200AXC 36Mbit NoBL SRAM, 200 MHz, 3.2 ns

MPNCY7C1460AV33-200AXC
Obsolete

Cypress NoBL™ synchronous SRAM, 36Mbit (1M x 36), 200 MHz clock frequency, 3.2 ns access time, parallel interface, 3.135V–3.6V supply, 100-LQFP (14x20mm), 0°C to 70°C operating temperature.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1460AV33-200AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency200 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time3.2 ns
Memory size36Mbit
Memory formatSRAM
Case100-LQFP
Memory organization1M x 36

Product details

Obsolete — sourcing path for this 36 Mbit NoBL SRAM

200 MHz clock, 3.2 ns access — what it buys you

This is a 36 Mbit synchronous SRAM organized 1M x 36, clocked at 200 MHz with a 3.2 ns access time. For a wide data-path buffer (36-bit word) in a networking or telecom line card, that means sustained throughput without the bus-turnaround penalty a conventional synchronous SRAM would incur.

Package and supply — 100-LQFP, 3.3 V core

The parallel memory interface is a standard 36-bit address/data bus; no serial or DDR conversion needed.

Frequently asked questions

Is CY7C1460AV33-200AXC obsolete?

Yes, the CY7C1460AV33-200AXC is listed as Obsolete by the manufacturer. No official replacement part number is provided in the record.

What is the replacement for CY7C1460AV33-200AXC?

No official replacement or successor order code is recorded for this part. If you need a pin-compatible alternative within the same Cypress NoBL family, a parametric search across 100-LQFP, 3.3 V, 36 Mbit synchronous SRAMs may yield a candidate — but no direct cross-reference is documented here.

What is the clock frequency and access time of CY7C1460AV33-200AXC?

The clock frequency is 200 MHz and the access time is 3.2 ns. These are the headline timing specs: the 200 MHz clock sets the bus rate, and the 3.2 ns access time defines how quickly data appears on the outputs after the address is presented.