NoBL synchronous SRAM — 167 MHz, 36Mbit, x36 width
The CY7C1460AV33-167BZC is a 36Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) series, organized 1M x 36 and clocked at 167 MHz. The x36 word width maps directly to 36-bit DSP or processor memory buses — one chip covers the full data path without byte-lane multiplexing. Access time is 3.4 ns, which sets the setup/hold window for the memory controller. At 167 MHz the bus cycles at 6 ns period — the 3.4 ns access leaves roughly 2.6 ns of timing margin before the next rising edge, enough for a typical FPGA or ASIC memory interface with derating.
Production has ended; the only channel to source CY7C1460AV33-167BZC today is the independent spot market, broker inventory, or excess-stock holders.
Supply range is 3.135V to 3.6V, a standard 3.3V nominal rail with ±5% tolerance. The parallel memory interface means the bus is direct-connect to a memory controller; no serialisation overhead. For a 36-bit bus, that is 36 data lines plus address and control — a 165-ball BGA is the natural footprint for that pin count.