36Mbit NoBL synchronous SRAM — 3.4 ns access, 167 MHz clock
It delivers a 3.4 ns access time and supports a 167 MHz clock, enabling back-to-back read/write operations without dead cycles — critical for high-throughput data buffers in networking, telecom, and video processing equipment.
No Bus Latency — why it matters for the bus
The NoBL architecture eliminates the turnaround cycle required by traditional synchronous SRAMs when switching from read to write (or write to read). On a 167 MHz bus, that saved cycle is 6 ns per transaction — which accumulates quickly in burst-oriented applications like packet buffering or cache tag memory.