The NoBL architecture eliminates the dead bus cycle between read and write operations that standard synchronous SRAMs require, allowing back-to-back transactions at full clock rate.
The 167 MHz clock rate sets the maximum data throughput at 167 million transfers per second on a 36-bit wide bus. The 3.4 ns access time from clock edge to data valid is the parameter that determines setup margin at the controller side. With a 6 ns clock period (1/167 MHz), the 3.4 ns access leaves roughly 2.6 ns for PCB trace delay and receiver setup — tight but workable with controlled impedance routing and matched-length traces. Designs migrating from a slower synchronous SRAM should verify that the controller's input timing budget closes at this access time.
Infineon lists the CY7C1460AV33-167AXC as Obsolete. No factory last-time-buy window remains open. Availability and pricing vary by date-code spread and condition — sealed reels with consistent date-codes are preferred.
Housed in a 100-lead TQFP (14x20 mm body), surface-mount.