36 Mbit NoBL synchronous SRAM — 2.6 ns access at 250 MHz
It delivers a 2.6 ns access time while clocking at 250 MHz, eliminating dead cycles between read and write turns on the bus. That makes it a fit for high-throughput packet buffers, cache tag stores, and DSP lookup tables where back-to-back transactions matter.
Housed in a 165-ball FBGA (15x17 mm), surface-mount only.
