36Mbit NoBL synchronous SRAM — 200 MHz, 3.2 ns access
The CY7C1460AV25-200BZXI is a 36 Mbit synchronous SRAM from Infineon's NoBL (No Bus Latency) series, organized as 1M x 36. It clocks at 200 MHz with a 3.2 ns access time, meaning the memory can deliver a new data word every clock cycle without dead cycles between read and write turns — critical for high-throughput data buffers in networking or test equipment. The 36-bit wide data bus (1M x 36) suits systems that need a 32-bit data word plus parity or ECC bits in a single access — common in telecom line cards and high-reliability storage controllers.
Supply rails and temperature range
Operates from 2.375 V to 2.625 V — a tight 2.5 V nominal core supply that keeps dynamic power predictable.
165-FBGA package — rework reality
Housed in a 165-ball FBGA (15x17 mm) — a fine-pitch BGA that requires a hot-air rework station and a pre-bake profile if the moisture-sensitive level is exceeded. No socket option; the board must be laid out for the 1.0 mm ball pitch typical of this footprint. Not a field-swappable part without a reflow oven.