36Mbit synchronous SRAM at 133 MHz
The CY7C1443KV33-133AXI is a 36Mbit synchronous SDR SRAM organized as 2M x 18 bits, clocked at 133 MHz with a 6.5 ns access time. The 18-bit word width suits DSP coefficient tables or packet-header lookup buffers where 16-bit data plus parity or tag bits ride the same bus without packing overhead.
Infineon lists the CY7C1443KV33-133AXI as Obsolete. The 100-TQFP package and 133 MHz speed grade narrow the field of drop-in alternatives. Any replacement must match the 100-pin LQFP footprint, the 3.3V supply rail, and the synchronous SDR interface at 133 MHz.
Industrial temperature and supply margin
The 3.135V–3.6V supply range provides 0.465V of margin below the nominal 3.3V rail, enough to ride through a 10% droop on a lightly regulated bus.