133 MHz synchronous SRAM with a 6.5 ns access window
It runs on a 133 MHz clock and delivers a 6.5 ns access time, which means the memory can sustain back-to-back reads at the full bus rate without wait states in most pipeline designs. The wide 36-bit word suits DSP engines, network processors, or any system that wants a single-chip data bus without byte-lane muxing.
The 3.135V to 3.6V supply rail keeps it compatible with 3.3V nominal systems while allowing margin during cold-crank or brownout conditions.
165-ball LBGA — footprint and handling
Housed in a 165-ball LBGA (15 mm x 17 mm body), the part is a surface-mount BGA. For high-volume reflow, check whether your assembly house can handle tray-fed pick-and-place or if a reel request is needed. The 1.0 mm ball pitch is standard for this density, but the BGA footprint demands careful PCB layout for signal integrity at 133 MHz.
Infineon lists the CY7C1441KV33-133BZM as Active.
