36 Mbit synchronous SRAM for wide-bus, high-reliability systems
It uses a single-data-rate (SDR) pipeline architecture clocked at 133 MHz, with a 6.5 ns access time from clock rise.
At 133 MHz the part delivers a 7.5 ns cycle time. The 6.5 ns access time from the rising clock edge leaves roughly 1 ns of setup margin before the next cycle — tight enough that the board-level trace delay and clock skew must be budgeted during timing closure. This is a pipelined synchronous SRAM: the address is registered on the first clock edge, and data appears on the following edge. There is no asynchronous read path, so the system controller must manage the pipeline latency.
1M x 36 organization — wide data bus fit
The 36-bit word width maps directly to a 32-bit data bus plus four parity or ECC bits, or to a 36-bit DSP data path without external muxing. The 36 Mbit density suits moderate-depth FIFO buffers, look-up tables, or packet memory in networking equipment. The parallel interface uses standard synchronous control signals (chip enable, write enable, output enable, burst control) — no serialisation overhead.
Military temperature range — screening for hi-rel programs
The 100-TQFP package is a plastic, surface-mount construction — not hermetic — so the buyer should verify that the program's moisture-sensitivity and outgassing requirements accept a plastic package before committing the BOM. The active lifecycle status means no last-time-buy risk for new designs.
Supply rail and decoupling considerations
At 133 MHz the dynamic current draw is significant; the datasheet recommends a 0.1 µF ceramic capacitor per supply pin, placed as close to the package as possible. The 100-TQFP has a 0.5 mm pitch — ensure the PCB fab can route the fine-pitch traces to the SRAM without via stubs that degrade signal integrity on the data bus.