36Mbit synchronous SRAM at 133 MHz
The CY7C1441KV33-133AXIT is a 36Mbit synchronous SRAM organised as 1M x 36 bits, clocked at 133 MHz with a 6.5 ns access time from the clock edge.
Access time and bus timing margin
At 133 MHz the clock period is 7.5 ns; a 6.5 ns access time leaves 1 ns of setup margin before the next clock edge. That margin shrinks with temperature and voltage derating, so the PCB layout must keep the clock-to-data trace skew under 0.5 ns to avoid hold-time violations.
Active production and ordering posture
Infineon lists the CY7C1441KV33-133AXIT as Active, meaning it is still in regular production with no announced end-of-life.