36Mbit synchronous SDR SRAM — 133 MHz pipeline buffer
The Infineon CY7C1441AV33-133AXCT is a 36Mbit synchronous SRAM organized as 1M x 36 bits, clocked at 133 MHz with a 6.5 ns access time.
133 MHz clock, 6.5 ns access — timing margin for the bus
The 133 MHz clock yields a 6.5 ns access time. The 1M x 36 organization matches a 36-bit data bus directly.
