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Infineon Technologies CY7C1420KV18-333BZXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1420KV18-333BZXI 36Mbit DDR-II SRAM, 333 MHz

MPNCY7C1420KV18-333BZXI
End of Life

Infineon Technologies CY7C1420KV18-333BZXI, 36Mbit synchronous DDR-II SRAM, 1M×36 organization, 333 MHz clock, 1.7V–1.9V supply, 165-FBGA (13×15mm), tray, -40°C to 85°C.

$44.6875Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1420KV18-333BZXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage1.7V ~ 1.9V
Clock frequency333 MHz
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTray
TechnologySRAM - Synchronous, DDR II
Memory size36Mbit
Memory formatSRAM
Case165-LBGA
Memory organization1M x 36

Product details

36 Mbit DDR-II SRAM at 333 MHz — what the clock rate means for the bus

The CY7C1420KV18-333BZXI is a 36 Mbit synchronous DDR-II SRAM organized as 1M × 36 bits. The 333 MHz clock drives a double-data-rate interface, meaning data transfers on both edges of the clock for an effective 666 MT/s on the memory bus. For a network processor or FPGA cache line that needs deterministic read-write latency without refresh cycles, this is the throughput ceiling — the part delivers a new 36-bit word every 1.5 ns in burst mode.

Supply rails and temperature grade — the operating envelope

The core supply runs from 1.7 V to 1.9 V, which is the standard DDR-II SRAM Vdd range. The I/O supply is separate on this family — the datasheet specifies VddQ at the same 1.7 V–1.9 V level, so the entire interface operates at the same rail.

Frequently asked questions

What is the memory organization and interface of this SRAM?

It is organized as 1M × 36 bits with a parallel DDR-II synchronous interface. The 333 MHz clock delivers 666 MT/s on the data bus, and the 36-bit word width suits wide data paths in networking or FPGA applications.