DDR-II SRAM for high-throughput cache and buffer applications
The Cypress CY7C1420AV18-200BZCT is a 36 Mbit DDR-II synchronous SRAM organized as 1M x 36, clocked at 200 MHz. The device is volatile SRAM in the synchronous DDR-II family, designed for high-bandwidth data buffering and cache memory in networking, telecom, and test equipment where read-write turnaround must be minimized.
At 200 MHz, the DDR-II interface transfers data on both clock edges, effectively doubling the data rate. For a 36-bit-wide bus, that delivers up to 14.4 Gbps of raw bandwidth. The 1M x 36 organization suits systems needing a wide word without concatenating multiple narrower parts — one chip covers a 36-bit memory bus at a single address depth.
165-ball FBGA — layout and rework notes
The supplier device package is 165-FBGA (15x17).
The CY7C1420AV18-200BZCT is marked obsolete by Cypress (now Infineon).