CY7C1418BV18-250BZC is officially classified as Obsolete by Infineon Technologies.
Memory organization and clock speed — what the 250 MHz buys
Organised as 2M words by 18 bits (36Mbit total), this DDR II+ synchronous SRAM clocks at 250 MHz. The double-data-rate architecture transfers data on both rising and falling edges of the clock, effectively doubling the throughput per pin versus a single-data-rate part at the same frequency — a meaningful edge for high-bandwidth pipeline buffers in networking or test equipment.
Package and board-fit — 165-FBGA
Housed in a 165-ball fine-pitch BGA (FBGA) with a body size of 15 mm x 17 mm (supplier device package 165-FBGA).